We propose a partitioned-bus architecture with a variable-width-bus scheme to reduce power consumption in bus lines in VLSIs. The partitioned-bus architecture (horizontal partitioning) restricts bus driving range to minimal, while the variable-width-bus scheme (vertical partitioning) uses additional tag lines so as to automatically indicate effective bus width with-out driving unnecessary bus lines depending on data to be transferred. Applying this method to a general purpose microprocessor, we demonstrate 30% and 35% power consumption reduction in bus lines, respectively for the partitioned-bus architecture and the variable-width-bus scheme, compared with the conventional bus architecture. Combining the both together, we show about 55% power consumption reduction in bus lines for typical applications. Increase in chip area for this architecture is about 30% compared with the conventional bus architecture.

We present a formula of short-circuit power dissipation for static CMOS logic gates. By representing short-circuit current by a piece-wise linear function and considering a current flowing from input node to output node through gate capacitances, the accuracy is improved significantly. The error of our formula in a CMOS inverter is less than 15% from circuit simulation in many cases of our experiments. A improved circuit simulation technique for short-circuit power dissipation is presented. Since this formula calculate the short-circuit power dissipation accurately and quickly, it will be applied to power sensible CAD tools.

This paper describes a study to determine if a current-mode circuit is useful as an analog circuit technique for realizing submicron mixed analog-and-digital MOS LSIs. To examine this, we designed and circuit simulated a new current-mode ADC bit-block for a 3 V, 10-bit level, 20 MHz ADC with a pipeline architecture and with full current-mode approach. A new precision current-mode sample-and-hold circuit which enables operation of a bit block at a clock speed of 20 MHz was developed. Current mismatches caused by the poor output impedance of a device were also decreased by adopting a cascode configuration throughout the design. Operation with a 3 V power supply and a 20 MHz clock speed in a 3-bit A/D configuration was verified through circuit simulation using standard CMOS 0.6 µm device parameters. Gain error, mismatch of current, and linearity of the bit block with changing threshold voltage of a device were carefully examined. The bit block has a gain error of 0.2% (10-bit level), a linearity error of less than 0.1% (more than 10-bit level), and a current mismatch of DAC current sources in a bit cell of 0.2 to 0.4% (more than 8-bit level) with a 3 V power supply and 20 MHz clock speed. An 8-to 9-bit video-speed pipeline ADC can be realized without calibration. This confirms that the current-mode approach is effective.

This paper surveys trends in and prospects for low power LSI circuits technologies for portable terminal equipment, in which low-voltage operation of LSIs will be emphasized because this equipment will be battery-powered. Since this brings about serious operation speed degradation of LSIs, however, it will become more and more important how to operate them faster under low-supply voltage. We propose two new circuit techniques that make it possible to operate LSIs at high speed even when the supply voltage is very low (1-2 V corresponding to one or two battery cells). The new low-voltage RF LSI circuit technique, developed using silicon bipolar technology and using a novel current-folded mixer architecture for the modulator, result in a highly linear modulator that operates at 2 V. Its power consumption is less than 2/3 that of previously reported ICs. And for a low voltage baseband LSI we propose the multi-threshold CMOS (MTCMOS) technique, which uses two sets of threshold-voltage levels so that the LSI can operate at high speed when driven by a 1-V power supply. The multi-threshold CMOS architecture enabled us to create LSIs that operate faster than conventional CMOS circuits using high-threshold-voltage MOSFETs. When operating with a 1-V power supply, our LSIs are three times faster than the conventional ones.

This paper describes a new, low power 16-bit Digital Signal Processor (DSP). The DSP has a double-speed MAC mechanism, an accelerator for Viterbi decoding, and a block floating section which contribute to lower power consumption. The double-speed MAC can perform two multiply and accumulate operations in one instruction cycle. Since MAC operations are so common in digital signal processing, this mechanism can reduce the average clock frequency of the DSP resulting in lower power consumption. The Viterbi accelerator and block floating circuitry also reduce the clock frequency by minimizing the number of required cycles needed to be executed. The DSP was fabricated using a 0.8 µm CMOS 2-aluminum layer process technology to integrate 644 K transistors on a 9.30 mm9.09 mm die. It can realize an 11.2 kbps VSELP speech CODEC while consuming only 70 mW at 3.5 V Vdd.

A new high performance digital signal processor (DSP) that lowers power consumption, reduces chip count, and enables system cost savings for wireless communications applications was developed. The new device contains high performance, hard-wired functionality with a specialized instruction set to effectively implement the worldwide digital cellular standard algorithms, including GSM, PDC and NADC, and also features both full rate and future half rate processing by software modules. The device provides a wider operating voltage ranging from 1.5 V to 5.5 V using 5 V process based on the market requirement of 5 V supply voltage, even though a power supply voltage in most applications will be shifted to 3 V. Several circuits was newly developed to achieve low power consumption and high speed operation at both 5 V and 3 V process using the same data base. The device also features over 50 MIPS of processing power with low power consumption and 100 nA stand-by current at either 3 V or 5 V. One remarkable advantage is a flexible CPU core approach for the future spin-off devices with different ROM/RAM configurations and peripheral modules without requiring any CPU design changes. This paper describes the architecture of a lower power and high speed design with effective hardware and software modules implementations.

A new low-power and high-speed CMOS interface circuit is proposed in which signals are transmitted by means of impulse voltage. This mode of transmission is called impulse transmission. Although a termination resistor is used for impedance matching, the current through the output transistors and the termination resistor flows only in transient states and no current flows in stable states. The output buffer and the termination resistor dissipate power only in transient states, so their power dissipation is reduced to 30% that of conventional low-voltage-swing CMOS interface circuits at 160 MHz. The circuit was fabricated by 0.5 µm CMOS technology and was evaluated at a supply voltage of 3.3 V. Experimental results confirm low power of 4.8 mW at 160 MHz and high-speed 870 Mb/s error free point-to-point transmission.

This paper describes a 600 mV single-chip MPEG2 video decoder, implemented in a 0.5 µm triple metal CMOS technology, which operates with a 3.3-volt power supply. To achieve low power consumption, a low power dual-port RAM has been developed utilizing a selective bit line precharge scheme to reduce bit line current which is suitable for use in the bit-slice array commonly found in parametric ASIC RAM macro modules. This architecture and a non-DC current sense amp make the RAM's read power consumption one-third of that of a conventional dual-port RAM. Various techniques such as multiple-clock architecture and a system clock independent from a display clock make a system clock frequency as low as possible. The video decoder has a syntax parser, so that it can handle the higher syntactic elements of MPEG2 bit streams without any host processor and decode the Main profile at Main level of MPEG2 bit streams.

In this paper, we propose a register file with data bypassing function. This register file bypasses data using data bypassing units instead of functional units when actual operation in functional units such as ALU is unnecessary. Applying this method to a general purpose microprocessor with benchmark programs, we demonstrate 50% power consumption reduction in functional units. Though length of bus lines increases a little due to an additional hardware in register file, as buses are not driven when data is bypassed, power consumption in bus lines is also reduced by 40% compared with the conventional architecture.

High speed GaAs ICs (Integrated Circutis) using FETs (Field Effect Transistors) are reported. As the fabricating techniques, ion implantation processes for both 0.5 µm and 0.2 µm gate FETs using W/Al refractory metal and 0.2 µm recessed gate process with MBE grown epitaxial wafers are shown. These fabrication processes are selected depending on the circuit speed and the integration level. The outline of the circuit design and the examples of ICs, which are developed for 10 Gb/s optical communication systems, are also shown with the obtained characteristics.

Low-power circuit techniques for size-configurable SRAM macrocells with wide range of operating frequency are presented. Synchronous specification is employed to drastically reduce the power dissipation for low-frequency applications. Dynamic circuits applied to bitliness and sense circuits contribute to the reduction of power dissipation. To enhance the high-end limitation of operating frequency, a latch-type fast sense circuit and an accurate activation-timing control technique for size-configurable memory macrocells are proposed, and a special CMOS-level input buffer is devised to enable the minimum cycle time of fast synchronous memory macrocells to be evaluated with conventional LSI-test systems. A memory macrocell using these techniques was fabricated with 0.5-µm CMOS technology. Its power consumption strongly depends on the operating frequency, and at 3-MHz suitable for codeless telephone applications is less than 5% that of an asynchronous SRAM designed with full-static CMOS circuits. Its maximum operating frequency at 3.3-V in 100-MHz.

The paper ptoposes a method to synthesize low-power control-logic modules by combining transistor-size optimization and transistor layout. Transistor sizing and layout work synergistically to achieve power/area optimization. Transistor size minimization provides more spaces for layout to be compacted. Layout compaction results in shorter wire length (i.e. smaller load capacitance), which allows transistors to become smaller. The details of transistor sizing and layout compaction are also described. When applied to circuits with up to 10,000 transistors, the optimizer reduced the average transistor size to one eighth while maintaining the same delay. The power dissipation is cut to half even when wiring capacitances are dominant.

In this paper, the power dissipation issue is considered in the gate sizing procedure. In order to observe the tradeoff among area, delar and power dissipation in a circuit, gate sizing algorithms which can minimize power under delay constraints or minimize area under power and delay constraints are formulated. Experiments are performed to investigate the properties of area–power–delay tradeoff in the gate sizing procedure.

A contact-less cell with high capacitive-coupling ratio (HiCR) of 0.8, which is programmed and erased by Fowler-Nordheim (F-N) tunneling, has been developed for single 3 V power-supply 64 Mbit and future flash memories. A 1.50 µm2 cell area is obtained by using 0.4 µm technology. The HiCR cell structure is realized by 1) self-aligned definition of small tunneling regions underneath the floating-gate side wall and 2) an advanced rapid thermal process for 7.5 nm-thick tunnel-oxynitride. The internal-voltages used for PROGRAM and ERASE are8 V and 12 V, respectively. The use of low positive internal-voltages results in reducing total process step numbers compared with reported memory cells. The HiCR cell also realizes low power and fast random access with a single 3 V power-supply.

This paper proposes a new fully-digitalized π/4-shift QPSK modulator consisting of a digital pulse shaping filter and a baseband quadrature modulator. By employing a novel digital filter configuration, the required filter memory is reduced to just 6.25% of the conventional one. Moreover, since the proposed baseband modulation scheme does not employ analog mixers or an analog 90 divider, a very accurate, high-stable and compact modulator is realized. It is shown that the proposed scheme achieves excellent low power consumption characteristics and is more suitable for digital LSIC implementation of personal communication terminals than a direct RF modulation scheme and an analog IF modulation scheme.

An improved array architecture to realize fast access, low power dissipation, and wide operating margin, for the 16 Mbit DRAM is proposed. A high speed access is obtained by the fully embedded sense drive scheme for the RAS access time (tRAC), and the special page mode with the hierarchical I/O data bus lines and multi-purpose-register (MPR) for the column address access time (tCAA). A low power dissipation and wide operating margin are obtained by the improved twisted-bit-line (TBL) architecture with double dummy canceling. The 16 Mb DRAM using these architectures has 38 ns tRAC, 14 ns tCAA and 75 mA power dissipation at the typical condition.

This paper describes a new 0.5-µm MOS current mode Logic (MCML) circuit that operates at 1.2 V, while maintaining high-speed performance, comparable with that of bipolar current mode circuits. An MCML circuit consists of differentially operating MOS transistors and a constant current source. Its performance at low voltage is compared with that of a CMOS circuit and bipolar current mode circuits. At 1.2 V, the MCML circuit has 90% the delay time of a CMOS circuit at 3.3 V. Delay times of CML and ECL circuits are 80% and 67% of that of the MCML circuit, respectively. Power of a 0.5-µm 500-MHz MCML circuit at 1.2 V, however, is 29%, 67% and 46%, of that of CMOS at 3.3 V, CML at 1.8 V and ECL at 2.6 V, respectively. Power-delay products of 500-MHz CMOS, CML and ECL circuits (normalized by the MCML circuit power-delay product) are 3.8, 1.2 and 1.5, respectively. MCML circuits can be used to construct any logic circuits. High-speed compact circuits are feasible, because MCML circuits output complementary signals. The delay time of an MCML full adder is only 200 ps. This is three times faster than that of a 3.3-V CMOS full adder. An MCML circuit has good characteristics and is widely applicable to logic circuits, so it is a useful circuit for producing sub-GHz processors.